An Intrinsic Gettering Process to Improve Minority Carrier Lifetimes in Mos and Bipolar Silicon Epitaxial Technology

JO Borland; M Kuo; J Shibley; B Roberts; R Schindler; T Dalrymple

doi:10.1520/STP32643S

SYMPOSIA PAPER Published: 01 January 1984

STP32643S

An Intrinsic Gettering Process to Improve Minority Carrier Lifetimes in Mos and Bipolar Silicon Epitaxial Technology

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Improvements in silicon epitaxial layer lifetime for CMOS P on P+ and N on N+ as well as bipolar N on P-epi technologies have been observed through the application of a four-step pre-epitaxial heat treatment to activate the intrinsic gettering mechanism in the substrate wafer prior to CVD epitaxial growth. Denuded zones 15 to 70 microns deep with bulk internal gettering sites were achieved and epilayer surface shallow etch pits were not detected on the gettered epi-wafers. Minority carrier lifetime (τ) on gettered epi-wafers showed an improvement in τ by as much as three orders of magnitude.

Author Information

Borland, JO

Applied Materials, Inc., Santa Clara, CA

Kuo, M

National Semiconductor, Santa Clara, CA

Shibley, J

National Semiconductor, Santa Clara, CA

Roberts, B

National Semiconductor, Santa Clara, CA

Schindler, R

Wacker-Chemitronic, Burghausen, West Germany

Dalrymple, T

Wacker Siltronic Corp., Portland, Ore.

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Details

Developed by Committee: F01

Pages: 49–62

DOI: 10.1520/STP32643S

ISBN-EB: 978-0-8031-4915-1

ISBN-13: 978-0-8031-0403-7

An Intrinsic Gettering Process to Improve Minority Carrier Lifetimes in Mos and Bipolar Silicon Epitaxial Technology

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